During the manufacture of modern integrated circuits, advanced photomasks are used to print integrated-circuit (IC) features with dimensions significantly less than the wavelength of light used in the optical lithography. Such advanced photomasks embody one or more resolution enhancement techniques (RETs), notably, optical proximity correction (OPC), sub-resolution assist features (SRAFs, also known as scattering bars (SBs)), and phase-shifting masks (PSM).
The layouts of these photomasks are designed automatically by an electronic design automation (EDA) computer program, which uses as an input a nominal chip layout originated by an earlier-executed set of EDA tools. The photomask layout-producing computer program may be referred to more specifically as a resolution enhancement (RE) program and not only produces an RE photomask design, but can also be commanded to produce an RE simulated layout that approximates the IC layout that the RE photomasks seek to produce. The RE simulated layout varies from the nominal layout according to differences that are unavoidable because of the inherent computational complexity of the RE photomask design problem. This unavoidable difference has been termed “error.” It may be noted that the RE simulated layout not only has error with respect to the nominal layout but is also suboptimal in the sense that if infinite computer time was available an optimal RE simulated layout matching the nominal layout as closely as possible could be produced by the RE program. The differences between the RE simulated layout and the nominal layout include error and suboptimality, which are herein collectively termed as the “RE difference.” There are also differences between the RE simulated layout and the eventual layout of the ICs manufactured by the masks designed by the RE program, due to inaccuracies in the RE program's modeling of the lithographic process, as well as to manufacturing errors.
Currently, the configuration and execution of the RE program is designed simply to arrive at an RE simulated layout that is as close as possible to the nominal layout, given the computer resources available. There appears to have been no suggestion of altering the starting conditions of the RE program to take advantage of opportunities to improve on the nominal layout, when possible, or to avoid differences with the nominal layout that would be particularly harmful. Such improvements and differences could affect the fabricated integrated circuit's performance, power, process window and/or manufacturing yield. In today's IC design and manufacturing process, the lack of RE program responsiveness to critical design aspects can cause severe problems.
The EDA tools used to originate the nominal layout use “guardbands” to ensure that the design will function correctly even if the worst expected error (e.g., a 6σ error) occurs for any particular feature in the realization of the nominal layout on the manufactured IC. The RE differences add to the error budget that determines the setting of the guardbands. The fact that the RE programs now run with no effort to bias the RE differences in a constructive manner forces EDA tools to guardband potential RE differences in a symmetric fashion. For example, if the RE program cannot guarantee that placement of a given feature's edges will be within a tolerance of less than five nanometers from that feature's edges in the nominal layout, then EDA tools will guardband the nominal layout dimension of the feature by at least +10 and −10 nanometers (since each of two opposite sides of the feature can be located by up to five nanometers from its nominal position).
The potentially harmful impact of symmetric guardbanding can be readily seen from the following examples. First, if a given transistor device has leakage power minimization as its most critical quality, then it would be advantageous that the result of the RE program be an edge location on the outer periphery of the tolerance band that is supplied as a starting condition to the RE algorithm. With current practices, however, the edge location could be anywhere in the symmetrically placed tolerance band, forcing the EDA tool to guardband so that the eventual IC will function even if the gate is as small as it would be if it just met the inner tolerance. The forced accommodation of this worst-case outcome creates inefficiencies in the nominal layout that are carried through to the finished IC. Moreover, the objective of building a gate that possesses the critical quality of leakage power minimization is likely to go unmet.
Second, there are also transistor devices that are setup-timing critical, i.e., the signal delay through the device cannot increase without jeopardizing the correctness of the IC's timing. For a setup-critical device, symmetric guardbanding forces the EDA tools to accommodate the worst-case signal delay that would result if the outer tolerance was just met. Again, this creates inefficiencies at every stage in the process that carries through to the final, manufactured IC. Also, the objective of building a gate that possesses the critical quality of signal delay minimization is likely to go unmet.
Third, feature density alters the effect of manufacturing process variability on feature qualities of an IC. In most lithographic processes, dense lines tend to print larger (i.e., with larger “critical dimension”) with variation in focus, while isolated lines tend to print smaller. Isolated lines, therefore, are more likely to suffer “open” faults (i.e., breaks in the lines) if on metal layers, and more likely to suffer increased off-current (i.e., leakage) if on the poly layer, in the presence of defocus variation in the manufacturing process. On the other hand, dense lines are more likely to suffer “short” faults (i.e., the unwanted electrical bridging of two distinct lines) if on metal layers, and more likely to have increased off-current (i.e., leakage) and reduced on-current (i.e., drive strength) if on the poly layer, in the presence of defocus variation in the manufacturing process. These differing tendencies are not noted in current practice when running RE programs.
In present-day IC design-to-manufacturing flows, there is a lack of any asymmetric guidance to the RE program based on the need for a feature to meet a critical quality. This failing decreases the quality of today's RE simulated layouts, which results in loss of performance and parametric yield in manufactured ICs.